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ASU has been engaged for over two years in shaping the design of the National Network for Microelectronics Research and Development — also called the Microelectronics Commons — which is the $2B portion of the funds appropriated by the CHIPS and Science Act that will be managed by the Department of Defense. On November 30, DoD released the Microelectronics Commons Request For Solutions (RFS), which solicits up to nine Regional Hubs. Hubs are “networks of regional entities with lab prototyping capabilities and sources of microelectronics talent for onshore, lab-to-fab transition of semiconductor technologies.”

ASU intends to lead a Regional Hub proposal that includes at least Arizona and New Mexico, and leverages its microelectronics design, fabrication and metrology strengths. Sandia National Lab, which has a 180 nm rad-hard CMOS line, will be a strategic partner in our Hub and will also serve with ASU as a split-fab Core.

Learn more about the Microelectronics Commons and ASU’s Regional Hub plans.

To build out our proposed solution, ASU is requesting solutions from faculty who would participate in the Hub leadership team as either Capability Area Leads or Project Leads. These two functions — developing enabling capabilities and leading projects that leverage those capabilities to achieve technology successes — have complementary roles in the success of the Hub. Capability Area Leads, both at ASU and at partner entities within the Hub, will be responsible for developing state-of-the-art resources that facilitate rapid prototyping of new technologies. Project Leads will lead project teams, which may draw in experts from across the Hub, to create prototypes at the system or sub-system level in one or more of the six DoD application areas.

Faculty experts who have visions for either a Capability Area or Project are asked to respond to this solicitation per the guidelines below. Selected faculty will serve as co-investigators or key personnel for ASU’s Regional Hub proposal. In addition to representing their own compelling vision, it is important that these leaders also represent a vision inclusive of their peers at ASU, as we expect that the Hub will be large and will facilitate the research and development activities of a sizable cross-section of ASU’s faculty.

To apply, please submit a statement, no longer than a page in length, to the limited submissions application site by 8 a.m. on Monday, December 19, 2022, that describes the following:

Capability Area Lead (five anticipated):

  • Your vision for microelectronics capability leadership at ASU in circuit design, new materials (for CMOS + X), power/RF devices, heterogeneous integration and advanced packaging, or metrology. What capabilities do we have and which would you propose developing?
  • The ASU team in this capability area (contributing faculty) and potential partners that you recommend adding to the Regional Hub to strengthen the capability area (these could be universities, labs, or companies, but equipment and software manufacturers are expected to be key to strengthening capability areas).

Project Lead (at least three anticipated):

  • Your vision for a future system or sub-system within the six DoD application areas and how it could be prototyped using the ASU-led Regional Hub and the Cores within the Microelectronics Commons. Please refer to the descriptions of the desired end states of the six application areas within Attachment C of the RFS. The proposed project should be large enough in scope (e.g., tens of millions of dollars) to require technical innovations in several capability areas and a sizable team.
  • The ASU team for this project (contributing faculty) and potential partners that you recommend adding to the Regional Hub to fill expertise gaps needed to complete the project (these could be universities, labs, or companies).

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