Transportation Seminar: Time in cyber-physical systems flier

Download the flier

Please join us at the ASU Transportation Seminar on Thursday, January 31, 2019, where Aviral Shrivastava, associate professor at ASU and head of the Compiler and Microarchitecture Labs (CML), will present a seminar titled, “Time in cyber-physical systems.”

Time in cyber-physical systems
Presented by Aviral Shrivastava, associate professor, Arizona State University

Thursday, January 31, 2019 
Noon–1:15 p.m.
College Avenue Commons (CAVC), room 559, Tempe campus [map]

Light refreshments will be served. Event is open to the public.

This seminar is webcast live to a worldwide audience. Access the live webcast and archive of previous seminar recordings.

About the talk

Cyber-Physical systems are those that tightly integrate physical and computational systems. One of the big challenges in distributed cyber-physical systems is establishing a common notion of time between the physical world and the computational system. Many modern CPS, especially industrial automation systems, require the actions of different computational systems to be synchronized at much higher rates than is possible through ad hoc designs. Fundamental research is needed in synchronizing clocks of computing systems to a higher degree, and even if the clocks are synchronized, designing CPS nodes so that they can perform actions in a synchronized manner is challenging. We need to find ways to specify distributed CPS applications, ways to specify and verify timing requirements on distributed CPS, confident top-down design methodologies that can ensure the system meets its timing requirements in the first go, dynamically creating and dissolving timing domains using differently build components, and much more. In this talk, I will present some of the work that we have done, and some of the ideas that we want to pursue in order to solve the challenge of confident and simplified CPS design (from the timing perspective). We believe that confident CPS design is possible only when the timing requirements of CPS are specified in the application itself, and not as a separate document. It should not be a list of separate requirements, but must be married to the application specification in as natural a way as possible.

About the speaker

Prof. Aviral Shrivastava is associate professor at Arizona State University, where he has established and heads the Compiler and Microarchitecture Labs (CML). He received his doctorate and master’s in information and computer science from the University of California, Irvine, and bachelor’s in computer science and engineering from Indian Institute of Technology, Delhi. He is a 2011 NSF CAREER Award recipient, and recipient of 2012 Outstanding Junior Researcher in CSE at ASU. His works have received several best paper nominations, including at DAC 2017, and a best student paper award at VLSI 2016. Professor Shrivastava’s research lies in the broad area of “Software for Embedded and Cyber-Physical Systems.” More specifically, Professor Shrivastava is interested in topics around i) Compilers and microarchitectures for heterogeneous and many-core computing, ii) Protecting computation from soft errors and iii) Precise timing for Cyber-Physical Systems. His research is funded by NSF, DOE, NIST and several industries including Microsoft, Raytheon Missile Systems, Intel, Nvidia etc. He serves on the organizing and program committees of several premier embedded system conferences.

Comments are closed.

  • Features

  • Follow us on Twitter

  • Fulton Engineering on Social Media

  • In the Loop

    In the Loop is an online news site for the faculty and staff of the Fulton Schools of Engineering at ASU.