Learn about new processes used for fault-localization and Signal Temporal Logic Specifications.
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Invited Talk: Localizaing faults in Simulink models using STL
Thursday, November 1, 2018
11 a.m.
Brickyard (BYENG) 420, Tempe campus [map]
Abstract
Fault-localization is a very tedious and time-consuming activity in the design of complex Cyber-Physical Systems (CPS). The task requires expert knowledge of the system in order to discover the cause of the fault. In this talk, Manjunath presents a new procedure that aids designers in debugging Simulink hybrid system models, guided by Signal Temporal Logic (STL) specifications.
The proposed approach relies on three main components:
- A monitoring and a trace diagnostics procedure that checks if a tested behavior satisfies or violates an STL specification localize time segments and interfaces variables contributing to the property violations.
- A slicing procedure that maps these observable behavior segments to the internal states and transitions of the Simulink model
- A spectrum based fault-localization method that combines the previous analysis from multiple tests to identify the internal states and/or transitions that are the most likely to explain the fault.
About the speaker
Niveditha Manjunath is a doctoral candidate at AIT Austrian Institute of Technology and is affiliated with the Vienna University of Technology. Her research interests are in fault-oriented V&V methods for CPS from concept to component design, and in particular in system diagnostics and fault localization. She is extending AMT monitoring tool with the system diagnostics capabilities.
She holds a master’s degree from Chemnitz University of Technology, Germany.
