Monday, March 23, 2015
11 a.m – noon
Goldwater Center 487, Tempe campus [map]
Extreme scaling imposes enormous challenges, such as increased variability and soft-error vulnerability, on the resilience of VLSI circuits and systems. For coping with those threats, we have been developing a VLSI platform that can realize a dependable circuit with required level of reliability. The platform achieves variability resilience at circuit-level by on-chip performance monitoring and variability compensation by localized body biasing. Architecture-level resilience to soft-errors is accommodated in a mixed-grained reconfigurable array that can configure functionality and reliability as well. Those properties have been experimentally verified by proof-of-concept chips fabricated in a 65nm process. Overview of the dependable VLSI platform with emphasis on the variability and soft-error resilience will be explained.
Hidetoshi Onodera received the B.E., M.E., and Dr. Eng. degrees in Electronic Engineering, all from Kyoto University, Kyoto, Japan. He joined the Department of Electronics, Kyoto University, in 1983, and currently a Professor in the Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University. His research interests include design technologies for Digital, Analog, and RF LSIs, with particular emphasis on low-power design, design for manufacturability, and design for dependability. Dr. Onodera served as the Program Chair and General Chair of ICCAD and ASP-DAC. He was the Chairman of the IPSJ SIG-SLDM (System LSI Design Methodology), the IEICE Technical Group on VLSI Design Technologies, the IEEE SSCS Kansai Chapter, and the IEEE CASS Kansai Chapter. He is currently the Chairman of IEEE Kansai Section. He served as the Editor-in-Chief of IEICE Transactions on Electronics and that of IPSJ Transactions on System LSI Design methodology.