Computer Systems Beyond Computing: Hybrid Energy Storage Systems
Neahyuck Chang, Seoul National University
Tuesday, July 2, 2013
11 a.m.-12:30 p.m.
Brickyard (BYENG) 210 [map]
Storage of excessive electrical energy can significantly mitigate demand and supply mismatch, provide quality spinning reserve, and thus reduce over-investment in the electricity generation facilities. So far, development of a better battery technology has been a main activity to develop high-performance energy storage systems (ESS). However, despite active research on new electrical energy storage device technologies (batteries or equivalents), it is not likely to have an ultimate high-efficiency, high power/energy capacity, low-cost, light-weight, and long-cycle life storage device in the near future. In other words, there is no single type of storage device that fulfills all these requirements.
Computer systems have been facing with the storage (memory) problem over decades; there is still no single type of memory device that provides high speed, low-cost, large-density, low-power, nonvolatile, long-endurance, etc. However, use of memory hierarchy, interconnect architectures and management policies, may take advantages of each memory device and hide its drawbacks.
We introduce hybrid electrical energy storage (HESS for short) that are comprised of multiple, heterogeneous storage banks connected via the charge transfer interconnect (CTI). We introduce both design time and runtime optimization of HESS. We formulate the HESS problems in the form of computer memory system design; interconnect architecture, FPGA placement and routing, and real-time task scheduling problems. This enables us to utilize profound systematic optimization methods that have been used in digital and computer systems design over decades.
Design time optimization includes HESS system architecture such as number of banks, types of banks, capacity of banks, CTI architectures, input and output converters, etc. We introduce various CTI architectures such as a shared bus, multiple bus, and network architectures, like computer interconnect architectures. We only take the advantages of each electrical storage device while hiding its weaknesses by proper runtime optimization because the HESS hardware architecture alone does not guarantee superior performance than that of conventional homogeneous ESS. HESS mandate elaborated runtime charge management policies like memory management policies for the memory hierarchy. We set up the hybrid electrical storage system management problems into charge allocation that determines a part of storage banks to be charged, charge replacement (discharge) that determines a part of storage banks to be discharged. The charge allocation and replacement are performed to achieve the best efficiency considering the power loss in the battery (or super capacitor) banks (IR loss, rate capacity effect, leakage, etc.) and the power loss in the charger and converters, which significantly varies by the input/output voltage and current. We provide charge migration that moves charge among the storage banks as the best set of banks for individual charge allocation and replacement process can be different in general.
Large-scale HESS should be able to perform various charge management tasks simultaneously. We formulate multiple charge transfer task management in the form of real-time energy-aware task scheduling in computer systems. Networked HESS brings up node placement and charge transfer task routing issues. We formulate these problems in the form of FPGA placement and routing problems. We demonstrate a HESS prototype with Li-Ion batteries, Lead-acid batteries and super capacitors.
Naehyuck Chang is a professor with the Department of Electrical Engineering and Computer Science and the Vice Dean of College of Engineering, Seoul National University, Seoul, Korea. His current research interests include low-power embedded systems, hybrid electrical energy storage systems and next-generation energy sources. He has served on the technical program committees in many EDA conferences, including DAC, International Conference on Computer Aided Design(ICCAD), International Symposium on Low Power Electronics and Design (ISLPED), DATE, CODES+ISSS, and ASP-DAC. He was a TPC (Co-) Chair of International Conference on Embedded and Real-Time Computing Systems and Applications 2007, ISLPED 2009, ESTIMedia 2009 and 2010, and CODES+ISSS 2012, and will serve as the TPC Chair of ICCD 2014, and the ASP-DAC 2015. He was the General Vice-Chair of ISLPED 2010, General Chair of ISLPED 2011, and ESTIMedia 2011. He was an Associate Editor of IEEE Transactions on Circuits and Systems-I, IEEE Transactions on Computer-Aided Design, ACM Transactions on Design Automation of Electronic Systems, and ACM Transactions on Embedded Computing Systems, Springer DAES, and was a Guest Editor of ACM Transactions on Design Automation of Electronic Systems in 2010, and ACM Transactions on Embedded Computing Systems in 2010 and 2011. He is the ACM SIGDA Chair, an ACM Distinguished Scientist and a Fellow of IEEE.