Computer architecture is undergoing, if not another revolution, then a vigorous shaking-up. The major chip manufacturers have, for the time being, simply given up trying to make processors run faster. Instead, they have switched to “multicore” architectures, in which multiple processors (cores) communicate directly through shared hardware caches, providing increased concurrency instead of increased clock speed.
As a result, system designers and software engineers can no longer rely on increasing clock speed to hide software bloat. Instead, they must somehow learn to make effective use of increasing parallelism. This adaptation will not be easy. Conventional synchronization techniques based on locks and conditions are unlikely to be effective in such a demanding environment. Coarse-grained locks, which protect relatively large amounts of data, do not scale, and fine-grained locks introduce substantial software engineering problems.
Friday, November 9, 2012
Brickyard Artisan Court 110
Maurice Herlihy has an A.B. in mathematics from Harvard University, and a Ph.D. in computer science from M.I.T. He served on the faculty of Carnegie Mellon University, on the staff of DEC Cambridge Research Lab, and is currently professor in the Computer Science Department at Brown University. He is an ACM Fellow, and is the recipient of the Dijkstra Prize in Distributed Computing in 2003 and in 2012, and the Goedel Prize in theoretical computer science in 2004. His 1993 paper inventing transactional memory won the 2008 ISCA influential paper award.